1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a complementary metal oxide semiconductor (CMOS) imager flush reset capability.
2. Description of the Related Art
FIG. 1 depicts a complementary metal oxide semiconductor (CMOS) imager with a “buried” or “pinned” photodiode (prior art). Conventionally, the image cell circuit includes four transistors and one photodiode. The pixel operation is divided into three main stages: reset, exposure, and reading.
(1) The reset stage: by turning on the reset and transfer (Tx) transistors, the photodiode capacitance is charged to a reset voltage. As for the case of the p+np buried photodiode shown in FIG. 1, the buried cathode (n) is totally depleted and set to the pinned voltage (Vpin).
(2) The exposure stage: with the absorption of light by the photodiode, electron and hole pairs are generated. The holes fill the depleted acceptor sites in the p-region, and the electrons fill the depleted donor sites in the n-region. The potential of the photodiode cathode decreases as the photoelectrons fills up at the donor sites.
(3) The reading stage: the pixel value is read out by a correlated double sampling (CDS) circuit. First, the select transistor and the reset transistor are turned on, the floating diffusion (FD) is set to high, and the output is set to the reference level. Then, the transfer transistor (Tx) is turned on, the accumulated photo-electrons in the photodiode are transferred to the FD. Photo-charges in FD are converted to the signal voltage by a source follower (SF) and read out as signal voltage level. The signal is constructed by subtracting the reference voltage level from the signal voltage level (see FIG. 2).
FIG. 2 is a timing diagram associated with of the pixel circuit of FIG. 1 (prior art). The advantage of using a buried photodiode in a CMOS imager sensor is that low dark currents may be obtained. If the charge in the buried n-cathode can be completely depleted during the reset, and the signal electrons in the buried n-cathode can be completely transferred during a CDS reading, then zero lag and zero reset noise can be achieved. Several device design parameters optimization such as: low voltage depleted diode, wide transfer transistor size, low threshold voltage, and high gate voltage on transfer transistor must be considered to achieve the complete transfer of the signal electrons in the buried n-cathode.
A color CMOS imager consists of pixels for detecting red, green, and blue colors using either an RGB color filter array to filter out unwanted spectrum, or by fabricating the photodiodes in a stack, so that the shallower photodiode detects the blue spectrum and the deepest photodiode detects the red spectrum. A pixel of a CMOS imager usually consists of one active pixel sensing (APS) circuit and one photodiode. An APS circuit is referred to herein as a “transistor set”. However, to increase the fill factor (the ratio of the photodiode area to the pixel area), a shared transistor set is used in modern CMOS imager fabrication. For a shared transistor set, two to four pixels (two to four photodiodes) typically share one transistor set.
The diode is first reverse biased to create a large depletion region where there are “no” free electrons and free holes. This is called the reset process. The depletion regions extend into both n- and p-regions, with ionized fixed positive charged donors and ionized fixed negative charged acceptors in the depleted n- and p-regions, respectively. When a photon is incident to the depletion region it excites an electron from the valance band to the conduction band. Equivalently, it generates an electron at the conduction band and a hole at the valence band. Due to the potential energy difference, the generated electrons flow to the n region and recombine with an ionized donor state, while the holes flow to the p-region and recombine with the negative charged accepter state. As a result, the space charge region loses negative charges and positive charges. The width of the space charge region varies as the voltage across the space charge region is reduced. In a four-transistor set (4T APS) of FIG. 1, the stored charge in the photodiode is transferred to the floating diffusion. The pixel circuit detects the voltage reduction as the output signal of the floating diffusion. The reduction in floating diffusion voltage is known as charge-to-voltage conversion. The accurate measurement of this voltage reduction is needed to reproduce the color of the object. In a 3T transistor set, or 3T APS cell circuit design, no transfer transistor and charge transfer process are needed. The pixel circuit detects the voltage reduction as output signal of the photo detector directly.
For the 3T transistor set, the sensing circuit detects the photodiode voltage, and the charge in the photodiode is never completely discharged. For the 4T transistor set, the charge transfer from the photodiode to the floating diffusion may not be completed and the charge in the floating diffusion is never completely discharged after the sensing circuit detects the signal. In either case, at the end of sensing, charges remain in the diode and floating diffusion. The amount of the remanding charge in each photodiode (3T), or in each photodiode and floating diffusion (4T) is not identical. As a result, the usual reset process that applies VDD to the gate and drain of the reset transistor, may not reset each photodiode (3T), or each photodiode and floating diffusion (4T) to the same voltage. The above-mentioned process is a “soft reset” and usually accompanies the so-called image lagging phenomenon. In order to avoid the image lagging phenomenon, a hard reset process is used to keep the reset transistor biased in the active region, or keep the gate voltage of the reset transistor higher than the drain voltage of the transistor by at least one threshold voltage. This solution takes care for the image lagging problem, but the reset voltage is low unless the gate of the reset transistor is biased higher than VDD, which may induce high voltage stress and result in device reliability failures. If the hard reset is followed up with a soft reset, which pre-charges the sensing circuit (including the bit line) to high voltage state, then fixed pattern noise can be minimized.
FIG. 3 is a schematic diagram of a pixel with a reset assist circuit and an associated timing diagram for the flushed reset of a pixel (prior art). As noted by Bedabrata Pain et al., the above-mentioned problems can be overcome by a flush hard reset followed by a soft reset process. The flushed-reset pixel approach eliminates the disadvantages of both the hard and soft-reset processes while retaining their respective advantages, without modification of the photodiode pixel layout. Therefore, the performance of the photodiode pixel is not altered. As shown, during the early stage of flush reset the φflush and φreset are on. The transistor MFR is off and MFR-out is on. The transistors MFdrop and MFR-out, MFR-load form a voltage divider. Therefore, the drain voltage of the reset transistor Mrst is lower than VDD. Since φreset is at VDD, the voltage at the cathode of the photodiode, VD is lower than VDD by at least one threshold voltage. After hard reset, the φflush is pulses low, and the drain voltage and the gate voltage of the reset transistor Mrst are VDD, and a soft reset begins.
However, the above-described circuit requires an addition independent bias voltage sources and operating signals. In this circuit there are a bias line, a flush pulse line, a Vload line and four (4) transistors added to the conventional active pixel sensing circuit.
It would be advantageous if the above-mentioned reset and the fixed pattern noise problems could be solved with a simple circuit and solitary control signal.